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low phase noise, fast settling, 6 ghz pll frequency synthesizer data sheet adf4196 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third par ties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respec tive owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features f ast settling, fractional - n pll architecture single pll replaces ping - pong synthesizers frequency hop across gsm band in 5 s with phase settled within 20 s 1 degree rms phase error at 4 ghz rf output digitally programmable output phase rf input range up to 6 ghz 3 - wire serial interface on - chip, l ow n oise d ifferential a mplifier phase noise figure of merit: ? 216 dbc/hz applications gsm/edge b ase stations phs b ase stations pulse doppler radar instrumentation and te st equipment beam - forming/phased a rray systems general description the adf4196 frequency synthesizer can be used to implement local oscillator s (lo) in the upconversion and down conversion sections of wireless receivers and transmitters. its architecture is specifically designed to meet the gsm/edge lock time require - ments for base stations , and t he fast settling feature makes the adf4196 suitable for p ulse doppler radar applications. the adf4196 consists of a l ow noise, digital phase frequency detector (pfd) and a precision differenti al charge pump. a differential amplifier convert s the differential charge pump output to a single - ended voltage for the external voltage controlled oscillator (vco). the sigma - delta ( - ) based fractional inter - polator, working with the n divider, allow s programmable modulus fractional - n division. additionally, the 4 - bit reference (r) counter and on - chip frequency doubler allow selectable reference signal (ref in ) frequencies at the pfd input. a complete phase - locked loop (pll) can be imple mented if the synthesizer is used with an external loop filter and a vco. the switching architecture ensures that the pll settles within the gsm time slot guard period, removing the need for a second p ll and associated isolation switches. this decreases the cost, complexity, pcb area, shielding , and characterization found on previous ping - pong gsm pll architectures. functional block dia gram 09450-001 n counter sw1 cp out+ cp out? sw2 reference data le 24-bit data register clk ref in a gnd 1 a gnd 2 d gnd 1 d gnd 2 d gnd 3 sd gnd sw gnd v dd dgnd lock detect r div n div sdv dd dv dd 1 dv dd 2 dv dd 3 av dd v p 1 v p 2 v p 3 r set output mux mux out ? + high-z phase frequency detector adf4196 fractional interpolator modulus reg fraction reg integer reg rf in+ rf in? 2 doubler 4-bit r counter /2 divider charge pump ? + + ? differential amplifier cmr ain? ain+ a out sw3 figure 1 .
adf4196 data sheet rev. b | page 2 of 28 table o f contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 transistor count ........................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptio ns ............................. 6 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 11 general description ................................................................... 11 reference input ........................................................................... 11 rf input stage ............................................................................. 11 pfd and charge pump .............................................................. 12 differential charge pump ......................................................... 12 fast lock timeout counters ..................................................... 12 differential amplifier ................................................................ 13 mux out and lock detect ......................................................... 13 input shift register .................................................................... 1 3 register map ................................................................................... 14 frac/int register (r0) latch map ....................................... 15 mod/r register (r1) latch map ............................................ 16 phase register (r2) bit latch map .......................................... 17 function register (r3) latch map ........................................... 18 charge pump register (r4) latch map .................................. 19 power - down register (r5) bit map ........................................ 20 mux register (r6) latch map and truth table ..................... 21 programming the adf4196 .......................................................... 22 worked example ........................................................................ 22 spur mechanisms ....................................................................... 22 power - up initialization ............................................................. 23 changing the frequency of the pll and the phase lookup table ............................................................................................. 23 applications information .............................................................. 25 local osc illator for a gsm base station ................................. 25 interfacing ................................................................................... 27 pcb design guidelines ............................................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 12/11 rev. a to rev. b changes to figure 10, figure 11, figure 13, and figure 14 ............................................................................................ 9 change to figure 31 ....................................................................... 17 10 /11 revision a : initial versio n
data sheet adf4196 rev. b | page 3 of 28 specifications av dd = dv dd 1, dv dd 2, dv dd 3 = sdv dd = 3 v 10%; v p 1, v p 2 = 5 v 10%; v p 3 = 5.35 v 5%; a gnd 1, a gnd 2 = d gnd 1, d gnd 2, d gnd 3 = 0 v ; r set = 2.4 k?; dbm referred to 50 ? ; t a = t min to t max , unless otherwise noted. operatin g temperature range = ? 40c to +85c. table 1. parameter min typ max unit test conditions/comments rf characteristics rf input frequency (rf in ) 0.4 6 ghz see figure 21 fo r input circuit rf input sensitivity ? 10 0 db m maximum allowable prescaler output frequency 1 750 mhz ref in characteristics ref in input frequency 300 mhz for f > 120 mhz, set ref/2 bit = 1 (register r1) ref in edge slew rate 300 v/ s ref in input sensitivity 0.7 v dd v p -p ac - coupled 0 to v dd v cmos compatible ref in input capacitance 10 pf ref in input current 100 a phase detector phase detector frequency 26 mhz charge pump i cp up/down high value 6.6 ma r set = 2.4 k? low value 104 a r set = 2.4 k? absolute accuracy 5 % r set range 1 4 k? nominally r set = 2.4 k? i cp three - state leakage 1 na i cp up vs. down matching 0.1 % 0.75 v v cp v p 1, v p 2, v p 3 ? 1.5 v i cp vs. v cp 1 % 0.75 v v cp v p 1, v p 2, v p 3 ? 1.5 v i cp vs. temperature 1 % 0.75 v v cp v p 1, v p 2, v p 3 ? 1.5 v differential amplifier input current 1 na output voltage r ange 1.4 v p 3 ? 0.3 v vco t uning r ange 1.8 v p 3 ? 0.8 v output n oise 7 nv/ hz at 20 khz offset logic i nputs input high voltage , v ih 1.4 v input low voltage , v il 0.7 v input current , i inh , i inl 1 a input capacitance , c in 10 pf logic outputs output high voltage , v oh v dd ? 0.4 v i oh = 500 a output low voltage , v ol 0.4 v i o l = 500 a power supplies av dd 2.7 3.3 v dv dd 1, dv dd 2, dv dd 3 av dd v v p 1, v p 2 4.5 5.5 v av dd v p 1, v p 2 5.5 v v p 3 5.0 5.65 v v p 1, v p 2 v p 3 5.65 v i dd (av dd + dv dd 1, dv dd 2, dv dd 3 + sdv dd ) 22 27 ma i dd (v p 1 + v p 2) 22 27 ma i dd (v p 3) 24 30 ma i dd power - down 10 a
adf4196 data sheet rev. b | page 4 of 28 parameter min typ max unit test conditions/comments sw1, sw2 , and sw3 on resistance sw1 and sw2 65 ? sw3 75 ? noise characteristics output 900 mhz 2 ? 108 dbc/hz at 5 khz offset and 26 mhz pfd f requency 1800 mhz 3 ? 102 dbc/hz at 5 kh z offset and 13 mhz pfd f requency phase noise normalized phase noise floor (pn synth ) 4 ? 216 dbc/hz at vco output with dither off , pll loop bandwidth = 500 khz normalized 1/f noise (pn 1_f ) 5 ? 110 dbc/hz measured at 10 khz offset, normalized to 1 g hz 1 choose a prescaler value that ensures that the frequency on the rf input is less than the maximum allowable prescaler frequency ( 7 5 0 mhz). 2 f ref in = 26 mhz; f step = 200 khz; f rf = 900 mhz; loop bandwidth = 40 khz. 3 f ref in = 13 mhz; f step = 200 khz; f rf = 1800 mhz ; loop bandwidth = 60 khz. 4 the synthesizer phase noise floor is estimated by measuring the in - band phase noise at the output of the vco and subtracting 20 log(n) (where n is the n divider value) and 10 log( f pfd ). pn synth = pn tot ? 10 log( f pfd ) ? 20 log(n). 5 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculating the 1 /f noise contribution at an rf frequency, f rf , and at an offset frequency, f, is given by pn = p 1_f + 10 log(10 khz/f) + 20 log( f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll ? . timing characteristi cs av dd = dv dd 1, dv dd 2, dv dd 3 = 3 v 10%; v p 1, v p 2 = 5 v 10%; v p 3 = 5.35 v 5%; a gnd 1, a gnd 2 = d gnd 1, d gnd 2, d gnd 3 = 0 v; r set = 2.4 k?; dbm referred to 50 ?; t a = t min to t max , unless otherwise noted. o perating temperature = ? 40c to +8 5 c. table 2. parameter limit description t 1 10 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 15 ns min clk high duration t 5 15 ns min clk low duration t 6 10 ns min clk to le setup time t 7 15 ns min le pulse width timing diagram 09450-002 clk data db23 (msb) db22 db1 (lsb) (control bit c2) db2 (lsb) (control bit c3) db0 (lsb) (control bit c1) le le t 2 t 4 t 5 t 3 t 7 t 6 t 1 figure 2 . timing diagram
data sheet adf4196 rev. b | page 5 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to g round ? 0.3 v to +3.6 v av dd to dv dd 1 , dv dd 2, dv dd 3, sdv dd ? 0.3 v to +0.3 v v p 1, v p 2, v p 3 to g round ? 0.3 v to +5.8 v v p 1, v p 2, v p 3 to av dd ? 0.3 v to +5.8 v digital i/o voltage to g round ? 0.3 v to v dd + 0.3 v analog i/o voltage to g round ? 0.3 v to v p 1, v p 2, v p 3 + 0.3 v ref in , rf in+ , rf in ? to g round ? 0.3 v to v dd + 0.3 v operating temperature range industrial ? 40c to +85c storage temperature range ? 65c to +125c maximum junction temperature 150c reflow soldering peak temperature 26 0c time at peak te mperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationa l section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. take proper precautions for handling and assembly. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package t ype ja unit 32- lead lfcsp (paddle soldered) 27.3 c/w transistor count this device includes 75,800 metal oxide semi conductor s (mos ) and 545 bipolar junction transisto r s (bjt ) . esd caution
adf4196 data sheet rev. b | page 6 of 28 pin configuration and function description s 09450-003 1 cmr 2 a out 3 sw3 4 a gnd 1 5 rf in? 6 rf in+ 7 a v dd 24 v p 2 23 r set 22 a gnd 2 21 d gnd 3 20 v p 1 19 le 18 dat a 17 clk 8 dv dd 1 adf4196 top view (not to scale) 9 d gnd 1 10 dv dd 2 1 1 ref in 12 d gnd 2 13 dv dd 3 14 sd gnd 15 sdv dd 16 mux out 32 v p 3 31 ain+ 30 cp out+ 29 sw1 28 sw gnd 27 sw2 26 cp out? 25 ain? pin 1 indic a t or notes 1. the exposed paddle must be connected to the ground plane. figure 3 . pin configuration table 5. pin function descriptions pin no. mnemonic description 1 cmr common - mode reference voltage for the output voltage swing of the differential amplifier. internally biased to thre e - fifths of v p 3. requires a 0.1 f capacitor to the ground plane . 2 a out differential amplifier output . this pin is the differential amplifier output to tune the external vco. 3 sw3 fast lock switch 3. this switch is c losed when the sw3 timeout counter i s active. 4 a gnd 1 analog ground. this is the ground return pin for the differential amplifier and the rf section. 5 rf in ? complementary input to the rf prescaler. this pin must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 6 rf in+ input to the rf prescaler. this small - signal input is ac - coupled to the external vco. 7 av dd power supply pin for the rf section. nominally 3 v. place a 100 pf decoupling capacitor to the ground plane as close as possible to this pin. 8 d v dd 1 power supply pin for the n divider. dv dd 1 s hould be at the same voltage as av dd . place a 0.1 f decoupling capacitor to the ground plane as close as possible to this pin. 9 d gnd 1 ground return pin for dv dd 1. 10 dv dd 2 power supply pin for the ref in buffer and r divider. nominally 3 v. place a 0.1 f decoupling capacitor to the ground plane as close as possible to this pin. 11 ref in reference input. this cmos input has a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k? . this input can be driven from a ttl or cmos crystal oscillator , or it can be ac - coupled. 12 d gnd 2 ground return pin for dv dd 2 and dv dd 3. 13 dv dd 3 power supply pin for the serial interface logic. nominally 3 v. 14 sd gnd ground return pin for the digital - modulator. 15 sdv dd power supply pin for the digital - modulator. nominally 3 v. place a 0.1 f decoupling capacitor to the ground plane as close as possible to this pin. 16 mux out multiplexer output. this multiplexer output allows the lock detect, t he scaled rf, or the scaled reference frequency to be accessed externally (s ee figure 35 for details ) . 17 clk serial clo ck input. d ata is clocked into the 24 - bit shift register on the clk rising edge. this input is a high impedanc e cmos input. 18 data serial data input. the serial data is loaded msb first with the three lsbs as the control bits. this input is a high impedance cmos input. 19 le load enable, cmos input. when le goes high, the data stored in the shift register is lo aded into the register that is selected by the three lsb s. 20 v p 1 power supply pin for the phase frequency detector (pfd) . nominally 5 v , v p 1 should be at the same voltage as v p 2. place a 0.1 f decoupling c apacitor to the ground plane as clos e as possibl e to this pin . 21 d gnd 3 ground return pin for v p 1. 22 a gnd 2 ground return pin for v p 2.
data sheet adf4196 rev. b | page 7 of 28 pin no. mnemonic description 23 r set connecting a resistor between this pin and gnd sets the charge pump output current. the nominal voltage bias at the r set pin is 0.55 v. the relationship betwe en i cp and r set is set cp r i 25 . 0 = therefore , with r set = 2.4 k? , i cp = 104 a. 24 v p 2 power supply pin for the charge pump. nominally 5 v, v p 2 should be at the same voltage as v p 1. place a 0.1 f decoupling capacitor to the ground plane as close as possible to this pin. 25 ain ? negative input pin for the differential amplifier. 26 cp out ? differential charge pump negative output pin. c onnect this pin to ain ? and the loop filter. 27 sw2 fast lock switch 2. this switch is closed to sw gnd wh en the sw1/ sw 2 timeout counter is active. 28 sw gnd ground for sw1 and sw2 s witches. c onnect this pin to the ground plane. 29 sw1 fast lock switch 1. this switch is closed to sw gnd when the sw1/ sw 2 timeout counter is active. 30 cp out+ differential charge pump p ositive output pin. c onnect this pin to ain+ and the loop filter. 31 ain + positive input pin for the differential amplifier. 32 v p 3 power supply pin for the differential amplifier. r ange s from 5.0 v to 5.5 v. place a 0.1 f decoupling capacitor to the gr ound plane as close as possible to this pin. v p 3 a lso requires a 10 f decoupling capacitor to the ground plane . ep exposed pad dle . the exposed pad dle must be connected to the ground plane.
adf4196 data sheet rev. b | page 8 of 28 typical performance characteristics 09450-038 freq. unit ghz keyword r param type s impedance 50 data format ma freq. mags11 angs11 0.5 0.8897 ?16.6691 0.6 0.87693 ?19.9279 0.7 0.85834 ?23.561 0.8 0.85044 ?26.9578 0.9 0.83494 ?30.8201 1.0 0.81718 ?34.9499 1.1 0.80229 ?39.0436 1.2 0.78917 ?42.3623 1.3 0.77598 ?46.322 1.4 0.75578 ?50.3484 1.5 0.74437 ?54.3545 1.6 0.73821 ?57.3785 1.7 0.7253 ?60.695 1.8 0.71365 ?63.9152 1.9 0.70699 ?66.4365 2.0 0.7038 ?68.4453 2.1 0.69284 ?70.7986 2.2 0.67717 ?73.7038 freq. mags11 angs11 2.3 0.67107 ?75.8206 2.4 0.66556 ?77.6851 2.5 0.6564 ?80.3101 2.6 0.6333 ?82.5082 2.7 0.61406 ?85.5623 2.8 0.5977 ?87.3513 2.9 0.5655 ?89.7605 3.0 0.5428 ?93.0239 3.1 0.51733 ?95.9754 3.2 0.49909 ?99.1291 3.3 0.47309 ?102.208 3.4 0.45694 ?106.794 3.5 0.44698 ?111.659 3.6 0.43589 ?117.986 3.7 0.42472 ?125.62 3.8 0.41175 ?133.291 3.9 0.41055 ?140.585 4.0 0.40983 ?147.97 figure 4. s-parameter data for the rf input 09450-006 frequency (hz) phase noise (dbc/hz) 1k 10k 100k 1m 10m ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 100m gsm900 rx setup, 40khz loop bw, dither off rf = 1092.8mhz, f ref = 26mhz, mod = 130 n = 42 4/130 integer boundary spur: ?103dbc @ 800khz figure 5. single-sideband (ssb) phase noise plot at 1092.8 mhz (gsm900 rx setup) vs. free running vco noise 09450-010 frequency (mhz) spur level (dbc) 1846 1859 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 1872 400khz spurs @ 25c 400khz spurs @ 85c dcs1800 tx setup with dither off, 60khz loop bw, 13mhz pfd. measured on eval-adf4193ebz1 board figure 6. 400 khz fractional spur levels across all dcs1800 tx channels over two integer multiples of the pfd reference 09450-005 frequency (ghz) rf sensitivity (dbm) 01234 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 765 4/5 prescaler 8/9 prescaler figure 7. rf input (rf in ) sensitivity 09450-007 frequency (hz) phase noise (dbc/hz) 1k 10k 100k 1m 10m ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 100m dcs1800 tx setup, 60khz loop bw, dither off rf = 1842.6mhz, f ref = 13mhz, mod = 65 dsb integrated phase error = 0.46 rms sirenza 1843t vco figure 8. single-sideband (ssb) phase noise plot at 1842.6 mhz (dcs1800 tx setup) 09450-011 frequency (mhz) spur level (dbc) 1846 1859 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 1872 600khz spurs @ 25c 600khz spurs @ 85c dcs1800 tx setup with dither off, 60khz loop bw, 13mhz pfd. measured on eval-adf4193ebz1 board figure 9. 600 khz fractional spur levels across all dcs1800 tx channels over two integer multiples of the pfd reference
data sheet adf4196 rev. b | page 9 of 28 09450-040 time (s) control voltage (v) ?1 0 1 2 3 4 5 9 8 7 6 5 4 3 2 1 0 v tune cp out+ cp out? dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193ebz1 evaluation board. timers: i cp = 28, sw1/sw2, sw3 = 35. frequency lock in wide bw mode @ 4s. figure 10 . v tune settling transient for a 75 mhz jump from 1818 mhz to 18 93 mhz with sirenza 1843t vco 09450-008 time (s) phase error (degrees) ?5 0 5 10 15 20 25 30 35 40 ?50 50 40 30 20 10 0 ?10 ?20 ?30 ?40 45 +25c +85c ?40c dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193ebz1 evaluation board with ad8302 phase detector. timers: i cp = 28, sw1/sw2, sw3 = 35. peak phase error < 5 @ 17.8s figure 11 . phase settling transient for a 75 mhz jum p fr om 1818 mhz to 1893 mhz (v tune = 1.8 v to 3.7 v with sirenza 1843t vc o ) 09450-012 cp out + / cp out ? voltage (v) i cp (ma) change pump mismatch (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?8 ?6 ?4 ?2 0 2 4 6 8 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 5.0 icp out + p, icp out ? p charge pump mismatch (%) normal operating range icp out + n, icp out ? n i up = | icp out + p | + | icp out ? n | i down = | icp out ? p | + | icp out + n | figure 12 . differential charge pump out put compliance range and charge pump mismatch with v p 1 = v p 2 = 5 v 09450-041 time (s) control voltage (v) ?1 0 1 2 3 4 5 9 8 7 6 5 4 3 2 1 0 v tune cp out? cp out+ dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193ebz1 evaluation board. timers: i cp = 28, sw1/sw2, sw3 = 35. frequency lock in wide bw mode @ 5s. figure 13 . v tune settling transient for a 75 mhz jump down from 1893 mhz to 1818 mhz (bottom of allowed tuning range ) with sirenza 1843t vco 09450-009 time (s) phase error (degrees) ?5 0 5 10 15 20 25 30 35 40 ?50 50 40 30 20 10 0 ?10 ?20 ?30 ?40 45 +25c +85c ?40c dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193ebz1 evaluation board with ad8302 phase detector. timers: i cp = 28, sw1/sw2, sw3 = 35. peak phase error < 5 @ 19.2s figure 14 . phase settling transient for a 75 mhz jump down from 1893 mhz to 1818 mhz (v tune = 3.7 v to 1.8 v with sirenza 1843t vco) 09450-013 frequency (mhz) control voltage (v) 1780 1800 1820 1840 1860 1880 1900 1920 1940 0 2 1 3 4 5 v p 1 = v p 2 = 5v v p 3 = 5.5v v cmr = 3.3v cp out? (= ain?) a out (= v tune ) cp out+ (= ain+) figure 15 . tuning range with a sirenza 1843t vco and a 5.5 v diff erential amp lifier power supply voltage
adf4196 data sheet rev. b | page 10 of 28 09450-042 frequency (hz) noise (nv/ hz) 1k 10k 100k 1m 1 10 100 1000 10m 7nv/ hz @ 20khz figure 16 . voltage noise density measured at the diff erential amp lifier output 09450-014 drain voltage (v) r on (?) 0 1 2 3 4 0 100 70 90 80 60 50 40 30 20 10 5 +85c sw3 ?40c +25c ?40c +25c +85c sw1, sw2 tuning voltage range figure 17 . on resistance of the sw1, sw2 , and sw3 loop filter switches 09450-044 phase code phase detector output (v) 0 0 1.8 1.5 1.2 0.9 0.6 0.3 130 117 104 91 78 65 52 39 26 13 measured using ad8302 phase detector y-axis scale: 10mv/degree rf = 1880mhz, pfd = 26mhz, mod = 130 x-axis scale: 2.77/step figure 18 . detected rf output phase for phase code sweep from 0 to mod 09450-045 interval between r0 writes should be a multiple of mod reference cycles (5s) for coherent phase measurements signal generator oscilloscope adf4193 eval board 104mhz 5dbm 10mhz ext ref 1880mhz 1805mhz 1880mhz rf out ref in signal generator inpa ad8302 evb vphs inpb figure 19 . test setup for phase lock time measurements
data sheet adf4196 rev. b | page 11 of 28 theory of operation general description the ad f4196 is targeted at gsm base station requirements, specifically to eliminate the need for ping - pong solutions . it can also be used in p ulse doppler r adar applications. the adf4196 works o n the basis of fast lock, using a wide loop bandwidth during a frequency change and narrowing the loop bandwidth when fre quency lock is achieved. widening the loop bandwidth is achieved by increasing the charge pump current. to maintain stability with the changing charge pump current, the adf4196 includes s witches that change the loop filter component values. the narrow loop bandwidth ensures that phase noise and spur spec ifications are met. a differential charge pump and loop fi lter top ology ensure that the fast lock time benefit obtained from widening the loop bandwidth is maintained when the loop is restored to narrow bandwidth mode for normal operation. reference input the reference input stage is shown in figure 20 . switch s w 1 and switch s w 2 are normally closed, and switch s w 3 is normally open. during power - down, s w 3 is closed, and s w 1 and s w 2 are opened to ensure that there is no loading of the ref in pin. the falling edge of ref in is the active edge at the positive edge triggered pfd. 09450-016 buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control figure 20 . reference input stage r counter and doubler the 4 - bit r counter allows the input reference frequency to be divided down to produce the reference clock to the pfd . a toggle flip - flop can be inserted aft er the r counter to provide an additional divide - by - 2. using this option has the add ed advantage of ensuring that the pfd reference clock has a 50/50 mark - to - space ratio. this ratio gives the maximum separation between the fast lock tim er clock, which is generated off the falling e dge of the pfd reference, and the rising edge, which is the active edge in the pfd. it is recommended that this toggle flip - flop be enabled for all even r divide values that are greater than 2 . the flip - flop mu st be enabled if divi ding down a ref in frequency that is greater than 120 mhz . an optional doubler before the 4 - bit r counter can be used for low ref in frequencies, up to 20 mhz. with these programmable options, reference division ratios from 0.5 to 30 bet ween ref in and the pfd are possible. rf input stage the rf input stage is shown in figure 21 . it is followed by a two - stage limiting amplifier to generate the cml clock levels needed for the prescaler. two pres caler options are a vailable : 4/5 and 8/9. select t he 8/9 prescaler for n divider values that are greater than 80. 09450-017 bias gener a t or 1.6v agnd a v dd 500? 500? rf in? rf in+ figure 21 . rf input stage rf n divider the rf n divider allows a fractional division ratio in the pll feedback path. the integer and f ractional parts of the division are programmed using separate registers, as shown in figure 22 and described in the int, frac, and mod relationship section . integer division ratios from 26 to 511 are allow ed , and a third - order - modulator interpolates the fractional value between the integer steps. 09450-018 third-order fractional interpolator frac value mod value int value rf n divider n = int + frac/mod from rf input stage to pfd n counter figure 22 . fractional - n rf divider int, frac, and mod relationship the int, frac, and mod values, programmed through the serial interface, make it possib le to generate rf output frequencies that are spaced by fractions of t he pfd reference frequency. the n divider value, shown inside the brackets of the following equation for the rf vco frequency (rf out ), is composed of an integer part (int) a nd a fraction al part (frac/mod). rf out = f pfd [ in t + ( frac/ mod )] (1) w here : rf out is the output frequency of the external vco . f pfd i s the pfd reference frequency. the value of mod is chosen to give the desired channel step with the available reference freque ncy. the n , program the int and frac words for the d esired rf output frequency. see the worked example section for more information.
adf4196 data sheet rev. b | page 12 of 28 pfd and charge pump the pfd takes inputs from the r divider and n divider and produces up and down outputs with a pulse width difference that is proportional to the phase difference between the inputs. the charge pump outputs a ne t up or down current pulse of a width that is equal to this difference, to pump up or pump down the voltage that is integrated i nto t he loop filter, which in turn increases or decreases the vco output frequency. if the n divider phase lags the r divider phase, a net up - current pulse is produced that increases the vco frequency (and , thus , the phase). if the n divider phase leads the r d ivider edge, a net down - current pulse is produced to reduce the vco frequency and phase . figure 23 is a simplified schematic of the pfd and charge p ump . the charge pump is made up of an array of 64 identical cells, each of which is fully differential. all 64 cells are active during fast lock , and only one cell is active during normal operation. because a single - ended control voltage is required to tune the vco, an on - chip differential - to - single - ended amplifier is provided for this p urpose. in addition, because the phase - lock ed loop controls only the differential voltage generated across the charge pump outputs, an internal common - mode feedback (cmfb) loop biases the charge pump outputs at a common - mode voltage of approximately 2 v. 09450-019 clr q d r divider n divider charge pum p arr a y [64:1] cmfb en[64:1] clr q d cp out+ cp out? figure 23 . pfd and differential charge pump simplified schematic differential charge pump the charge pump cell has a fully differential design for best up - to - down current matching (see figure 24) . good mat ching is essential to minimize the phase offset created when switching the charge pump curre nt from its high value (in fast lock mode) to its nominal value (in normal mode). to pump up, the up switches are on , and the pmos current source s out through cp out + , which increases the voltage on the external loop filter capacitors that are connected to cp out+ . similarly , the nmos current sink on cp out ? decreases the voltage on the external loop filter capacitors that are connected to cp out ? . therefore , the differe ntial voltage between cp out+ and cp out ? increases. to pump down, pmos current sources out through cp out ? and nmos current sinks in through cp out+ , which decreases the (cp out+ , cp out ? ) differential v oltage. the charge pump up/down matching is improved by a n order of magnitude over the conventional single - ended charge pump that depends on the matching of two different device types. the up/down matching in this structure depends on how a pmos matches a pmos , and how an nmos matches an nmos. 09450-035 v bias p p p n n up down down up v bias n cp out+ c pout? figure 24 . differential charge pump cell with external loop filter components fast lock timeout co unters t imeout counters, clocked at one - quarter of the pfd reference frequency, are provided to precisely control the fast locking operation (see figure 25 ). when a new frequency is programmed, the fast lock timers start and the pll locks into wide bandw idth mode with the 64 identical 100 a charge pump cells active (for a total of 6.4 ma). when the i cp counter times out, th e charge pump current is reduced to 1 by deselecting cells in binary steps over th e next six timer clock cycles, until only one 100 a cell is active. the switching of the charge pump current, from 6.4 ma to 100 a , equates to an 8 - to - 1 change i n loop ban dwidth ; when this happens, t he loop filter must be changed to ensure stability . t he sw1, sw2, and sw3 switches change the loop filter . the application s circuit shown in figure 37 shows how the switches can be used to reconfigure the loop filter time constants. they close to short out e xternal loop filter resistors during fast lock and open when their counters time out to restore the filter time constants to their normal values for the 100 a charge pump current. because it tak es six timer clock cycles to reduce the charge pump current to 1 , it is recomme nded that both sw itch timers be pro - grammed to the value of the i cp tim er plus 7 . 09450-036 sw1/sw2 timeout counter sw3 timeout counter i cp timeout counter en[64:1] 4 start f pfd sw3 a out sw2 sw gnd sw1 write to r0 charge pump enable logic figure 25 . fast lock timeout counters
data sheet adf4196 rev. b | page 13 of 28 differential amplifi er the inter nal, low noise, differential - to - single - ended amplifier convert s the differential charge pump output to a single - ended control voltage for the tuning port of the vco. figure 26 shows a simplified schematic of the differential ampli fier. the output voltage is equal to the differential voltage, offset by the voltage on the cmr pin , according to the following equation: v aout = (v ain+ ? v ain ? ) + v cmr (2) the cmr offset voltage is internally biased to three - fifths of v p 3, the differentia l amplifier power supply voltage, as shown in figure 26 . connect a 0.1 f capacitor to the ground plane from the cmr pin to roll off the thermal noise of the biasing resistors. 09450-020 ain? a out ain+ cmr v p 3 c ext = 0.1f 20k? 30k? 500? 500? 500? 500? figure 26 . diff erential am p lifier block diagram as shown in figure 15 , the differ ential amplifier output voltage behaves according to e quation 2 over a 4 v range from ~ 1.2 v min imum up to v p 3 ? 0.3 v maximum. how ever, fast settling is guaranteed over a tuning voltage range from 1.8 v up to v p 3 ? 0.8 v only . this range allow s sufficient room for overshoot in the pll frequency settling transient. noise from the differential amplifier is suppresse d inside the pll loop bandwidth. for loop bandwidths of >20 khz, the 1/f noise has a negligible effect on the pll output phase noise. outside the loop bandwidth, the fm noise of the differential amplifier modulates the vco. the passive filter network follo wing the differential amplifier (see figure 37) suppresses this noise contribution to below the vco noise from offsets of 400 khz and greater . this network has a negligible effect on lock time because it is bypassed when sw3 is clo sed while the loop is locking. mux out and lock detect mux out control the o utput multiplexer on the adf4196 allows the user to access various internal points on the chip. the state of mux out is controlled by b its[m4: m1] in the mux register. figure 35 shows the full truth ta ble; see figure 27 for a block diagram of the mux out circuit . 09450-021 r divider output n divider output serial data output d gnd dv dd control mux mux out logic low three-state output timer outputs digital lock detect logic high note: 1. not all mux out modes that are shown refer to the mux register. figure 27 . mux out circuit lock detect mux out can be programmed to provide a digital lock detect signal. digital lock detect is active high. its output goes high if there are 40 successive pfd cycles with an input error of <3 ns. for reliable lock detect operation with rf frequencies of <2 ghz, it is recomm ended that this threshold be increased to 10 ns by programming register r6. the digital lock detect goes low again when a new channel is programmed or when the error at the pfd input exceeds 30 ns for one or more cycles. input shift register the adf4196 serial interface includes a 24 - bit input shift register. data is clocked in , msb first , on each rising edge of clk. data from the shift register is latched into one of eight control registers, r0 to r7, on the r ising edge of l oad enable (le) the destination register is determined by the state of the three control bits : c3 (db2) , c2 (db1), and c1 (db0 ) in the shift register. db2, db1, and db0 are t he three lsbs, a s shown in the timing diagram in figure 2 . the truth table for these bits is shown in table 6 . figure 28 shows a summary of how the registers are programmed. table 6 . c3, c2, and c1 truth table control b its c3 (db2) c2 (db1) c1 (db0) register name register 0 0 0 frac/int r0 0 0 1 mod/r r1 0 1 0 phase r2 0 1 1 function r3 1 0 0 charge p ump r4 1 0 1 power - d own r5 1 1 0 m ux r6 1 1 1 test m ode r7
adf4196 data sheet rev. b | page 14 of 28 register map 09450-022 db23 f5 db22 f4 db21 0 db20 f2 db19 f1 db18 r4 db17 r3 db16 r2 db15 r1 db14 m12 db13 m11 db12 m10 db11 m9 db10 m8 db9 m7 db8 m6 db7 m5 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (0) db1 c2 (0) db0 c1 (1) dbb dbb dbb dbb dbb 4-bit rf r counter cp adj ref/2 reserved prescaler doubler enable 12-bit modulus control bits mod/r register (r1) db15 0 db14 p12 db13 p11 db12 p10 db11 p9 db10 p8 db9 p7 db8 p6 db7 p5 db6 p4 db5 p3 db4 p2 db3 p1 db2 c3 (0) db1 c2 (1) db0 c1 (0) dbb reserved 12-bit phase control bits phase register (r2) db15 0 db14 0 db13 0 db12 0 db11 0 db10 0 db9 0 db8 0 db7 0 db6 1 db5 f3 db4 1 db3 f1 db2 c3 (0) db1 c2 (1) db0 c1 (1) pfd polarity reserved cpo gnd reserved control bits function register (r3) db15 m13 db14 m12 db13 m11 db12 m10 db11 0 db10 0 db9 0 db8 0 db7 1 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (1) db1 c2 (1) db0 c1 (0) reserved mux out control bits sigma-delta and lock detect modes mux register (r6) db15 0 db14 0 db13 0 db12 0 db11 0 db10 0 db9 0 db8 0 db7 0 db6 0 db5 0 db4 0 db3 0 db2 c3 (1) db1 c2 (1) db0 c1 (1) reserved control bits test mode register (r7) db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (1) counter reset cp 3-state pd charge pump pd diff amp control bits power-down register (r5) db23 0 db22 0 db21 0 db20 0 db19 0 db18 0 db17 0 db16 0 db15 0 db14 1 db13 c9 db12 c8 db11 c7 db10 c6 db9 c5 db8 c4 db7 c3 db6 c2 db5 c1 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (0) 9-bit timeout counter reserved control bits timer select charge pump register (r4) dbb = double buffered bit(s) db23 n9 db22 n8 db21 n7 db20 n6 db19 n5 db18 n4 db17 n3 db16 n2 db15 n1 db14 f12 db13 f11 db12 f10 db11 f9 db10 f8 db9 f7 db8 f6 db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (0) db1 c2 (0) db0 c1 (0) 9-bit rf int value 12-bit rf frac value control bits frac/int register (r0) figure 28 . bit maps for reg ister r0 to register r7
data sheet adf4196 rev. b | page 15 of 28 frac/int register (r0) latch map 09450-023 db23 n9 db22 n8 db21 n7 db20 n6 db19 n5 db18 n4 db17 n3 db16 n2 db15 n1 db14 f12 db13 f11 db12 f10 db11 f9 db10 f8 db9 f7 db8 f6 db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (0) db1 c2 (0) db0 c1 (0) 9-bit rf int value 12-bit rf frac value control bits f12 0 0 0 0 . . . 1 1 1 1 f11 0 0 0 0 . . . 1 1 1 1 f10 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... f3 0 0 0 0 . . . 1 1 1 1 f2 0 0 1 1 . . . 0 0 1 1 f1 0 1 0 1 . . . 0 1 0 1 fractional value (frac) 0 1 2 3 . . . 4092 4093 4094 4095 n8 0 . . . 1 n7 0 . . . 1 n9 0 . . . 1 n6 0 . . . 1 n5 1 . . . 1 n4 1 . . . 1 n3 0 . . . 1 n2 1 . . . 1 n1 0 . . . 1 integer value (int) 26 . . . 511 0 frac < mod figure 29 . bit map for register r0 r0, the frac / int register, is used to program the synthesize r output frequency. on the pfd cycle following a write to r0, the n divider section is updated with the new int and frac values , and the pll auto matically enters fast lock mode. t he charge pump current is increased to its maximum value and remains at this value until the i cp timeout counte r times out; and the sw1, sw2, and sw3 switches close and remain closed until the sw1/ sw 2 and sw3 timeout counters time out. after all the registers are programmed during the initiali zation sequence (see table 9 ), a new channel can be program med by perform ing a write to r0. however, as described in the programming the adf4196 section, it may also be desirable to program the r1 and r2 register settings on a channel - by - channel basis. these settings are double buffered by the w rite to register r0. this means that , although the data is loaded through the serial interface on the respective r1 and r2 write cycles, the synthesizer is not updated with their data until the next write to register r0. control bits to select r0 , the fra c/int register, the three lsbs ( c3, c2, a nd c1) should be set to 0, 0, 0 . 9 - bit rf int value bits[db23 :db15] set the int value, which determines the integer part of the feedback division factor. all integer values from 2 6 to 511 a re allowed (s ee the worked example section ) . 12- bit rf frac value b its [db14:db3] set the numerator of the fraction that is input to the - modulator. this fraction , along with int, specifies the new frequency channel that the synthesizer locks to, as show n in the worked example section. frac values from 0 to mod ? 1 cover channels over a frequency range that is equal to the pfd reference frequency.
adf4196 data sheet rev. b | page 16 of 2 8 mod/r r egister (r1) latch map 09450-024 db23 f5 db22 f4 db21 0 db20 f2 db19 f1 db18 r4 db17 r3 db16 r2 db15 r1 db14 m12 db13 m11 db12 m10 db11 m9 db10 m8 db9 m7 db8 m6 db7 m5 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (0) db1 c2 (0) db0 c1 (1) 4-bit rf r counter cp adj ref/2 reserved prescaler doubler enable 12-bit modulus control bits 0 1 nominal adjusted cp adj f5 0 1 disabled enabled ref/2 f4 0 1 f2 4/5 8/9 prescaler 0 1 f1 doubler disabled doubler enabled doubler enable m12 0 0 0 . . . 1 1 1 1 m11 0 0 0 . . . 1 1 1 1 m10 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... m3 1 1 1 . . . 1 1 1 1 m2 0 1 1 . . . 0 0 1 1 m1 1 0 1 . . . 0 1 0 1 interpolator modulus value (mod) 13 14 15 . . . 4092 4093 4094 4095 r4 0 0 0 0 . . . 1 1 1 1 r3 0 0 0 1 . . . 1 1 1 1 r2 0 1 1 0 . . . 0 0 1 1 r1 1 0 1 0 . . . 0 1 0 1 rf r counter divide ratio 1 2 3 4 . . . 12 13 14 15 figure 30 . bit map for re gister r1 r1, t h e mod/r register , set s the pfd reference frequency and the channel step size, which is determined by the pfd frequency divided by the fractional modulus. note that the 12- bit modulus, the 4 - bit rf r counter, the doubler enable bits, ref/2, and cp adj are double buffered. they do not take effect until the next write to r0 ( the frac/int register) is complete. control bits register r1 is selected w it h c3, c2, and c1 set to 0, 0, 1. cp a dj when the cp adj bit is set to 1, the charge pump curren t is scaled up 25% from its nominal value on the next write to r0. when this bit is set to 0, the charge pump current remain s at its nominal value on the next write to r0. see the programming the adf4196 section for more informati on on how this feature can be u sed . ref/2 setting the ref/2 bit to 1 inserts a divide - by - 2 toggle flip - flop b etween the r counter and the pfd, which extends the maximum ref in input rate. reserved bit the r eserved b it , db21 , must be set to 0. prescaler (p /p + 1) the dual - modulus prescaler (p/p + 1), along with int, frac, and mod, determine the overall division ratio from rf in to the pfd input. operating at cml levels, it takes the clock from the rf input stage and divides it down for the counters. it is ba sed on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 3 ghz. therefore, when operating the adf4196 above 3 ghz, the prescaler must be set to 8/9. the prescaler limits the int valu e. if p = 4/5, then n min = 26. if p = 8/9, n min = 80 . doubler enable setting th e doubler enabler bit to 1 inserts a frequency doubler between ref in and the 4 - bit rf r counter. setting this bit to 0 bypasses the doubler. 4 - b it rf r counter the 4 - bit rf r co unter allows the ref in frequency to be divided down to produce the reference clock to the pfd. all integer v alues from 1 to 15 are allowed (s ee the worked example section ) . 12- bit modulus for a given pfd reference frequen cy, the fractional denomi nator or modulus sets the channel step resolution at the rf output. all integer val ues from 13 to 4095 are allowed. see t he programming the adf4196 section for a worked example and guid elines for selecting the value of mod .
data sheet adf4196 rev. b | page 17 of 28 phase register (r2) bit latch map 09450-025 db15 0 db14 p12 db13 p1 1 db12 p10 db 1 1 p9 db10 p8 db9 p7 db8 p6 db7 p5 db6 p4 db5 p3 db4 p2 db3 p1 db2 c3 (0) db1 c2 (1) db0 c1 (0) rese r ved 12-bit phase contro l bits p12 0 0 0 . . . 1 1 1 1 p1 1 0 0 0 . . . 1 1 1 1 p10 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... p3 0 0 0 . . . 1 1 1 1 p2 0 0 1 . . . 0 0 1 1 p1 0 1 0 . . . 0 1 0 1 phase value 1 0 1 2 . . . 4092 4093 4094 4095 1 0 phase value < mod figure 31 . bit map for register r2 r2, the phase register, is used to program the phase of the vco output signal. control bits register r2 is selected with c3, c2, and c1 set to 0, 1, 0 . 12- bit phase the 12- bit phase word sets the seed value of the - modulator. it can be programmed to any integer value from 0 to mod , where mod is the modulus value that is programmed in register r1 , bits [db14:db3] . as t he phase word is swept from 0 to mod , the phase of the vco output sweeps over a 360 range in steps of 360/mod. note that the phase bits are double buffered ; t hey do not take effect until the load enable of the next write to r0 ( the frac/int register). th us , to change the phase of the vco output frequency , it is necessary to rewrit e the int and frac values to register r0 following the write to register r2. the output of a fractional - n pll can settle to any one of the mod possible phase offsets with respect to the reference, where mod is the fractional modulus . t o keep the output at the same phase offset with respect to the reference, each time that particular output frequency is pro - grammed, the interval between writes to register r0 must be an integer mul tiple of mod reference cycles. t o keep the outputs of two adf4196 - based synthesizers phase coherent with each other (but not necessarily with the reference they have in common ) , t he write to register r0 on bot h chips must be performed during the same reference cycle. i n this case, t he interval between the r0 writes does not need to be an integer multiple of mod cycles. reserved bit set t he reserved bit, db15, to 0.
adf4196 data sheet rev. b | page 18 of 28 function register (r 3) latch map 09450-026 db15 0 db14 0 db13 0 db12 0 db11 0 db10 0 db9 0 db8 0 db7 0 db6 1 db5 f3 db4 1 db3 f1 db2 c3 (0) db1 c2 (1) db0 c1 (1) pfd polarity reserved cpo gnd reserved control bits 0 1 f1 negative positive pfd polarity 0 1 f3 cpo/cpo gnd normal cpo gnd figure 32 . bit map for register r3 r3, t he function register , needs to be programmed only during the initialization sequence (see table 9 ). control bits register r3 is selected with c3, c2, and c1 set to 0, 1, 1 . cpo gnd when the cpo gnd bit is low, the charge pump outputs are internally pulled to ground. this is invoked during the initiali - zation sequence to discharge the loop filter capacitors. for normal op eration, this bit should be set to 1 . pfd polarity set t h e pfd polarity bit t o 1 for positive polarity , and set it to 0 for negative polarity. reserved bits program the db15 to db6 reserved bits to a hexadecimal code of 0x 001 , and set the db4 reserved bit to 1.
data sheet adf4196 rev. b | page 19 of 28 charge pump registe r (r4) latch map 09450-027 db23 0 db22 0 db21 0 db20 0 db19 0 db18 0 db17 0 db16 0 db15 0 db14 1 db13 c9 db12 c8 db11 c7 db10 c6 db9 c5 db8 c4 db7 c3 db6 c2 db5 c1 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (0) 9-bit timeout counter reserved control bits timer select 0 0 1 1 f2 0 1 0 1 f1 sw1/sw2 sw3 i cp not used timer select c9 0 0 0 0 . . . 1 1 1 1 c8 0 0 0 0 . . . 1 1 1 1 c7 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... c3 0 0 0 0 . . . 1 1 1 1 c2 0 0 1 1 . . . 0 0 1 1 c1 0 1 0 1 . . . 0 1 0 1 timeout counter 0 1 2 3 . . . 508 509 510 511 xpfd cycles 0 4 8 12 . . . 2032 2036 2040 2044 delay s 1 0 0.15 0.30 0.46 . . . 78.15 78.30 78.46 78.61 1 delay with 26mhz pfd figu re 33 . bit map for register r4 r4, the charge p ump register, is used for programming the timers for loop filter switches. these switches help maintain the stability of the loop filter after boosting the charge pump current. contro l bits register r4 is select ed with c3, c2, and c1 (bits[db2:db0]) set to 1, 0, 0 . reserved bits for normal operation, s et the db23 to db14 reserved bits to a hex adecimal code of 0x 001. 9 - bit timeout counter these bits are used to program the fast lock tim eout counters. the counters are clocked at one - quar ter the pfd reference frequency; therefore, their time delay scales with the pfd frequency according to the following equation: delay ( s ) = ( timeout counter value 4)/( pfd frequency ) for example, if 35 is loade d with timer select = 00, with a 13 mhz pfd, sw1 and sw2 switch after the following: (35 4)/13 mhz = 10.8 s timer select the two timer select bit s select the timeout counter that is to be programmed. note that set ting up the adf4196 for correct operation requires setup of these three timeout counters : i cp , sw1/sw2, and sw3. t herefore , three writes to this register are required in the initialization sequence. table 7 shows examp le values for a gsm tx synthesizer with a 60 khz final loop bandwidth . see t he applications information section for more information. table 7 . recommended values for a gsm tx lo timer select timeout counter value time (s) with pfd = 13 mhz 10 i cp 28 8.6 01 sw3 35 10.8 00 sw1/sw2 35 10.8 on each write to r0, the timeout counters start. switch sw3 closes until the sw3 counter times out. similarly, the sw1 and sw2 switches close until the sw1/sw2 counter times out. when the i cp counter times out, the charge pump current is ramped down from 64 to 1 in six binary steps. it is recommended that the sw1/sw2 and sw3 timeout counter values be set equal to the i cp timeout counter value plus 7, as in the example shown in table 7 .
adf4196 data sheet rev. b | page 20 of 28 power - down register (r5) bit map 09450-028 db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (1) counter reset cp 3-state pd charge pump control bits pd diff amp 0 1 f4 0 1 f5 disabled enabled diff amp power-down 0 1 f2 normal operation 3-state enabled charge pump 3-state 0 1 f1 normal operation counter reset counter reset 0 1 f3 disabled enabled charge pump power-down figure 34 . bit map for register r5 r5, the power - d own register , can be used to power down the pll and differential amplifier sec tions. after power is initially applied, register r5 must be programmed to clear the power - down bits . then , before the adf4196 comes out of power - down , the r2, r1, and r0 registers must be programmed . control bits register r5 is s elected with c3, c2, and c1 set to 1, 0, 1 . power - down differential amplifier when the db7 and db6 bits are set to 1 , the differential amplifier is put into power - down. when db7 and db6 are set to 0 , normal operation resumes . power - down charge pump setting bit db5 to 1 activates a charge pump power - down , and the following events occur: ? all active dc current paths are removed, except for the differential amplifier. ? the r and n divider counters are forced to their load state conditions. ? the charge pump is po wered down with its outputs in three - state mode. ? the digital lock detect circuitry is reset. ? the rf in input is debiased. ? the reference input buffer circuitry is disabled. ? the serial interface remains active and capable of loading and latching data. for nor mal operation, set bit db5 to 0, followed by a write to r0. cp three - state when th e cp three - state bit is set to 1 , the charge pump outputs enter three - state. setting the cp three - state bit to 0 enables the charge pump outputs. counter reset whe n th e count er reset bit is set to 1, the coun ters are held in reset. for nor mal operation , set this bit to 0, followed by a write to r0.
data sheet adf4196 rev. b | page 21 of 28 m ux register (r 6) latch m ap and truth table 09450-029 db15 m13 db14 m12 db13 m11 db12 m10 db11 0 db10 0 db9 0 db8 0 db7 1 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (1) db1 c2 (1) db0 c1 (0) reserved mux out control bits sigma-delta and lock detect modes 0 1 1 m10 0 1 0 m11 0 0 0 all other states m12 0 0 1 m13 init state, dither off, 3ns lock detect threshold dither on 10ns lock detect threshold reserved sigma-delta modes 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 m4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 m3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 m2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 m1 3-state digital lock detect n divider output logic high r divider output reserved serial data output logic low r divider/2 output n divider/2 output reserved reserved i cp timeout signal sw1/sw2 timeout signal sw3 timeout signal reserved mux out figure 35 . bit map and mux out truth table for register r6 r6, the mux register, is used to program mux out , as well as - and lock detect modes. control bits r egister r6 is selected with c3, c2, and c1 set to 1, 1, 0 . - and lock detect modes bit db15 to bit db12 are used to reconfigure certain pll operating modes. in the initialization sequence after power is applied to the chip, the four bits must first be programmed to all zeros. this initializes the pll to a known state with dither off in the - modulator and a 3 ns pfd error threshold in the lock detect circuit. to turn on dither in the - modulator, a n additional write should be made to register r6 to program bits[db15:db12] = 0011 . however, for lowest noise operation, it is best to leave dither off. to change the lock detect threshold from 3 ns to 10 ns, perform a separate write to r6 t o program bits[ db15:db12] = 1001 . this separate write is needed for reliable lock detect operation when the rf frequency is <2 ghz. a write to r6 that programs bits [db15:db12] = 0000 returns operation to the default state with both dither off and a 3 ns lock detect thres hold. reserved bits for normal operation, t he reserved bits (bits[db11:db7] ) must be set to 00001. mux out modes these bits control the on - chip multiplexer, pin 16 (s ee figure 35 for the truth table ) . this pin is useful for diag nosis because it allows the user to look at various internal points of the chip, such as the r divider and the int divider outputs. in addition, it is possible to monitor the programmed timeout counter intervals on mux out . for example, if the i cp timeout c ounter is programmed to 65 (with a 26 mhz pfd), then following the next write to r0, a pulse width of 10 s is observed on the mux out pin. digital lock detect is available via the mux out pin.
adf4196 data sheet rev. b | page 22 of 28 programming the adf4196 the adf4196 can synthesize output frequencies with a channel step or resolution that is a fraction of the input reference fre - quency. for a given input reference frequency and a desired output frequ ency step, the first choice to make is the pfd reference frequency and t he mod value. after these are chosen , the desired output frequency channels are set by programming the int and frac values. worked example in this example of a gsm900 r x system, the r f output frequencies must be generated w ith channel steps of 200 khz. a reference frequency input (ref in ) of 104 mhz is available . the r divider setting that determines the pfd reference is shown in equation 3 . f pfd = ref in [(1 + d )/( r (1 + t ))] (3 ) wh ere : ref in is the input reference frequency . d is the doubler enable bit (0 or 1) . r is the 4 - bit r counter code ( 1 to 15) . t is the ref/2 bit (0 or 1) . the maximum pfd reference frequency of 26 mhz is chosen , and the following settings are programmed to g ive an r divider value of 4: ? doubler enable = 0 ? r = 2 ? ref/2 = 1 next , the modulus is chosen to allow fractional steps of 200 khz: mod = 26 mhz/200 khz = 130 (4 ) when the channel step is defined , e quation 5 shows how output frequenc y channels are programmed . rf out = [ int + ( frac/ mod ) ] f pfd (5 ) w here : rf out is the desired rf output frequency . int is the integer part of the division . frac is the numerator part of the fractional division . mod is the modulus or denominator part of the fractional division . thus , the frequency channel at 962.4 mhz is synthesized by programming the following values: int = 37 and frac = 2 . spur mechanisms the following section s describe the three different spur mechanisms that arise with a fractional - n synthesizer and how the adf4196 can best be programmed to minimize them. fractional spurs the fractional interpolator in the adf4196 is a third - order , - modulator (sdm) with a modulus mod t hat is programmable to any integer value from 13 to 4095. if dither is enabled, the minimum allowed value of mod is 50. the sdm is clocked at the pfd reference rate (f pfd ) , which allows pll output frequencies to be synthesized at a channel step resolution of f p fd /mod. with dither turned off, the quantization noise from the - modulator appears as fractional spurs. the interval between spurs is f pfd /l, where l is the repeat length of the code sequence in the digital - modulator. for the third - order modulator used in t he adf4196 , the repeat length depends on the value of mod, as shown in table 8 . table 8 . fractional spurs with dither off condition (dither off) repeat leng th spur interval mod is divisible by 2 but n ot by 3 2 mod channel step/2 mod is divisible by 3 but n ot by 2 3 mod channel step/3 mod is d ivisible by 6 6 mod channel step/6 all other divisors mod channel step with dither enabled, the repeat lengt h is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum look like broadband noise. this can degrade the in - band phase noise at the pll output by as much as 10 db. therefore, for lowest noise, dither off is a better choice, particularly when the fina l loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. the wide loop bandwidth range that is available with the adf4196 allows the use of dither in most applications. integer boundary spurs another mechanism for fractional spur creation involves interactions between the rf vco frequency and the reference frequency. when these frequencies are not integer related (which is the purpose of a fractional - n synthesizer) , spur sidebands appear on the vco output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer mu ltiple of the reference and the vco frequency. these spurs are attenuated by t he loop filter and are more noticeable on channels that are close to integer multiples of the refer ence , where the difference frequency c an be inside the loop bandwidth ( thus , the name integer boundary spurs ) . the 8:1 loop bandwidth switching ratio of the adf4196 makes it possible to attenuate all spurs to sufficiently low levels for most applications. the final loop bandwidth can be chosen to ensure that all spurs are far enough out of band and meet the lock t ime requirements with the 8 bandwidth boost. the programmable modulus and r divider of the adf4196 can also be used to avoid integer boundary channels. this option is described in the avoiding integer boundary channels section.
data sheet adf4196 rev. b | page 23 of 28 reference spurs reference spurs are generally not a problem in fractional-n synthesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop can cause a problem. one such mechanism is feedthrough of low levels of on-chip reference switching noise out of the rf in pins back to the vco, resulting in reference spur levels as high as ?90 dbc. these spurs can be suppressed below ?110 dbc by inserting sufficient reverse isolation, for example, through an rf buffer between the vco and rf in pins. also, take care in the printed circuit board (pcb) layout to ensure that the vco is well separated from the input reference to avoid a possible feedthrough path on the board. power-up initialization after applying power to the adf4196 for the first time, a 14-2530 sequence is recommended, as described in table 9. the divider and timer settings used in the example in table 9 are for a dcs1800 tx synthesizer with a 104 mhz ref in frequency. the adf4196 powers up after step 13 and locks to the pro- grammed channel frequency after step 14. table 9. power-up initialization sequence a and initialization sequence b step 1 register/ bits hex code description 1 r5 [7:0] 0xfd set all power-down bits. 2 r3 [15:0] 0x005b pfd polarity = 1, ground cp out+ /cp out? . wait 10 ms allow time for loop filter capacitors to discharge. 3 r7 [15:0] 0x0007 clear test modes. 4 r6 [15:0] 0x000e initialize pll modes, digital lock detect on mux out . 5a r6 [15:0] 0x900e 10 ns lock detect threshold, digital lock detect on mux out . 5b r6 [15:0] 0x000e add 16 pfd cycle delay after le before starting hop to next frequency. 6 r4 [23:0] 0x004464 sw1/sw2 timer = 10.8 s. 7 r4 [23:0] 0x00446c sw3 timer = 10.8 s. 8 r4 [23:0] 0x004394 i cp timer = 8.6 s. 9 r2 [15:0] 0x00d2 phase = 26. 10 r1 [23:0] 0x520209 8/9 prescaler, doubler disabled, r = 4, toggle ff on, mod = 65. 11 r0 [23:0] 0x480140 int = 144, frac = 40 for 1880 mhz output frequency. 12 r3 [15:0] 0x007b pfd polarity = 1, release cp out +/cp out? . 13 r5 [7:0] 0x05 clear all power-down bits. 14 r0 [23:0] 0x480140 int = 144, frac = 40 for 1880 mhz output frequency. 1 initialization sequence a includes step 5a and omits step 5b; initialization sequence b includes step 5b and omits step 5a. two initialization sequences are available for the adf4196 : initialization sequence a and initialization sequence b. one or the other must be selected. initialization sequence a consists of step 1 through step 14 in table 9, including step 5a (but not step 5b). (for initialization sequence b, step 5a is replaced by step 5b.) in initialization sequence a, the frequency hop starts immediately after the rising edge of le, whereas in initialization sequence b, the adf4196 waits 16 pfd cycles and then starts the hop. initialization sequence b reduces the overshoot of a frequency jump, but the start of a jump is delayed by 16 pfd cycles. figure 36 shows this phenomenon. 09450-136 time (s/div) v tune (v) 2.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 le initialization sequence a initialization sequence b figure 36. frequency jumps for initialization sequence a and initialization sequence b changing the frequency of the pll and the phase lookup table after the adf4196 is initialized, only a write to register r0 is required to program a new output frequency. the n divider is updated with the values of int and frac on the next pfd cycle following the le edge that latches in the r0 word. however, the settling time and spurious performance of the synthesizer can be further optimized by modifying the r1 and r2 register settings on a channel-by-channel basis. these settings are double buffered by the write to r0. this means that, although the data is loaded through the serial interface on the respective r1 and r2 write cycles, the synthesizer is not updated with the new data until the next write to register r0. register r2 can be used to digitally adjust the phase of the vco output relative to the reference edge. the phase can be adjusted over the full 360 range at rf with a resolution of 360/mod. in most frequency synthesizer applications, the actual phase offset of the vco output with respect to the reference is unknown and is irrelevant. in such applications, the phase adjustment capability of r2 can, instead, be used to optimize the settling time performance as described in the phase lookup table section.
adf4196 data sheet rev. b | page 24 of 28 phase looku p table the fast lock sequence of the adf4196 is initiated after the write to register r0. the fast lock timers are programmed so that after the pll has settled in to wide bandwidth mode, the charge pump current is reduced and the loop filt er resistor swit ches are opened, which reduce s the loop bandwidth . the reference cycle on which these events occur is determined by the values that are pre programmed into the timeout counters. the phase locking plots of figure 11 and figure 14 show that the lock time to final phase is dominated by the phase swing that occurs when the bandwidth is reduced. when the pll settles to its final frequency and phase , in wide bandwidth mode, this phase swing is the same regardles s of the size of the frequency jump of the synthesizer . the amplitude of the phase swing is related to the current flowing through the loop filter resistors on the pfd reference cycl e that open the sw1 and sw2 switches. in an integer - n pll, this current i s zero when the pll has settled. in a fractional - n pll , the current is zero , on average , b ut it varies from one reference cycle to the next, depending on the quantization error sequence output from the digital - modulator. becaus e the - modulator is all digital logic, cl ocked at the pfd reference rate for a given val ue of mod, t he actual quantization error on any given reference cycle is determined by the value of frac and the phase word with which the modul ator i s seeded , following the write to r0. by choosing an appropriate value of phase corresponding to the value of frac that is programmed on the next write to r0, the size of t he error current when the sw1 and sw2 switches are opened can be minimized. thu s, the phase swing that occurs when the bandwidth is reduced can be minimized. with dither off, the fractional spur pattern that is due to the quantization noise of the sdm also dep ends on the phase word with which the modulator is seeded . tables of optim ized frac and phase values for popular sw1/sw2 and i cp timer settings can be downloaded from the adf4196 product page. if using a phase tab le, first write the phase to double buffered register r2, and then wri te the int and frac values to register r0. avoiding integer boundary channels w hen program ming a new frequency, another option involves a write to register r1 to avoid integer boundary spurs. if the integer boundary spur level is too high, the integer boun dary can be moved away from the desired channel by reprogramming the r divider to select a different pfd frequency. for example, if ref in = 104 mhz and r = 4 for a 26 mhz pfd referenc e , and mod = 130 for 200 khz steps, the freque ncy channel at 910.2 mhz ha s a 200 khz integer bound ary spur because it is offset by 2 00 khz from 35 26 mhz. an alternative way to synthesize thi s channel is to set r = 5 for a 20.8 mhz pfd reference and mod = 104 for 200 khz steps. the 910.2 mhz channel becomes a 5 mhz offset fro m the nearest integer multiple of 20.8 mhz , and the 5 mhz beat note spurs are well attenuated by the loop. setting the double buffered db23 bit ( bit cp a dj in register r1) to 1 increases the charge pump current by 25%, which compensates for the 25% increas e in n with the change to the 20.8 mhz pfd frequency. this maintains constant loop dynamics and settling time performance for jumps between t he two pfd frequencies. clear t he cp adj bit when returning to 26 mhz - based channels. the register r1 settings tha t are required for integer boundary spur avoidance are all double buffered and do not become active on the chip until the next write to register r0. always ensure that register r0 is the last register written to when programming a new frequency. serial int erface activity the serial interface activity when pr ogramming the r2 or r1 register causes no noticeable disturbance to the synthesizer s settled phase or degradation in i ts frequency spectrum. thus, in a gsm applicatio n, serial interface activity can be performed during the active part of the data burst. because it takes only 10.2 s to program the three registers ( r2, r1, and r0 ) with the 6.5 mhz serial interface clock rate typically used, this program - ming can also be performed during the previous guard period with the le edge to latch i n the r0 data, delayed until it i s time to switch the frequency .
data sheet adf4196 rev. b | page 25 of 28 applications information local oscillator for a gsm base station figure 37 shows the adf4196 being used with a vco to produce the lo for a gsm1800 base station. for gsm, the ref in signal can be any integer multiple of 13 mhz, but the main requirement is that the slew rate be at least 300 v/s. the 104 mhz , 5 dbm input sine wave sho wn in figure 37 satisfies this requirement. recommended parameters for the various gsm/ dcs/p cs synthesizers are listed in table 10. table 10 . recommended setup parameters gsm900 dcs 1800/pcs1900 parameter tx rx tx rx loop bw 60 khz 40 khz 60 khz 40 khz pfd 13 mhz 26 mhz 13 mhz 13 mhz mod 65 130 65 65 dither off off off off prescaler 4/5 4/5 8/9 8/9 i cp timer 28 78 28 38 sw1, sw2, sw3 timers 35 85 35 45 vco k v 18 mhz/v 18 mhz /v 38 mhz/v 38 mhz/v loop bandwidth and pfd frequency a 60 khz loop bandwidth is narrow enough to attenuate the pll phase noise and spurs to the required level for a tx low. a 40 khz bandwidth is necessary to meet the gsm900 rx synthesizers particularly tough phase noise and spur requirements at 800 khz offs ets. to get the lowest spur levels at 800 khz offsets for rx, the - modulator should be run at the highest over - sampling rate possible. therefore, for gsm900 rx, a 26 mhz pfd frequency is chosen , a nd mod = 130 is required for 200 khz steps. because this value of mod is divisible by tw o, certain frac channels have a 100 khz fractional spur. this is attenuated by the 40 khz loop filter and , therefore , is not a concern. however, the 60 khz loop filter that is recommended for tx has a closed - loop response that peaks close to 100 khz. therefore, a 13 mhz pfd with mod = 65, which avoids the 100 khz spur, is the best choice for a tx synthesizer. dither dither off should be selected for the lowest rms phase error. prescaler the 8/9 presca ler should be selected for the dcs and p cs bands. the 4/5 prescaler allows an n divider range low enough to cover the gsm900 tx and rx bands with either a 13 mhz or 26 mhz pfd frequency. timer values for tx to comply with t he gsm sp ectrum due to switching require ments, the tx synthesizer should not switch frequency until the pa output power has ramped down by at least 50 db. if it takes 10 s to ramp down to this level, only the last 20 s of the 30 s guard period is availa ble for the tx synthesizer to lock to final frequency and phase. in fast lock mode, the tx loop bandwidth is widened by a factor of 8 to 480 khz and , therefore, the pl l achieves frequency lock for a jump across the entire band in <6 s. after this, the pa power can start to ramp up again, and the loop bandwidth can be restored to the final value. with the i cp timer = 28, the charge pump current reduction begins at ~8.6 s. when the sw1, sw2, and sw3 timers = 35, the current reaches its final value before th e loop filter switches open at ~10.8 s. with these timer values, the phase disturbance created when the bandwidth is reduced settles back to its final value by 20 s, in time for the start of the active part of the gsm burst. if faster phase settling is d esired with the 60 khz bandwidth setting, the timer values can be reduced further but should not be broug ht less than the 6 s that is required to a chieve frequency lock in wide bandwidth mode. timer values for rx the 40 khz rx l oop bandwidth is increased by a factor of 8 to approximately 320 khz during fast lock. with the rx timer values shown in table 10 , the bandwidth is reduced after ~12 s, which allows sufficient time for the phase disturbance to settle back before the start of the active part of the rx time slot at 30 s . as in the tx synthesizer case , faster rx settling can be achieved by reducing these timer values, their lower limit being determined by the time it takes to achieve frequency lock in wide bandwidth mode. in addition, the dcs and p cs rx synthesizers have relaxed 800 khz blocker specifications and , thus , can tolerate a wider loop bandwidth , which allows correspondingly faster settling. vco k v in general, the vco gain, k v , should be set as low as possible to mi nimize the reference and integer boundary spur levels that arise due to feedthrough mechanisms. when deciding on the optimum vco k v , a good choice is to allow 2 v to tune across the desired band, centered on the available tuning range. with v p 3 regulated t o 5.5 v 100 mv, the tuning range available is 2.8 v. loop filter components for good settling performance, it is important that capacitors with low dielectric absorption be used in the loop filter. ceramic npo c 0 g capacitors are a good choice for this ap plication. a 2% tolerance is recommended for loop filter capacitors and 1% for resistor s. a 10% tolerance is adequate for the inductor, l1.
adf4196 data sheet rev. b | page 26 of 28 adis impll support th e adf4193 loop fi lter design is supported on adis impll v2.7 or later. example files for popula r applications are available for download from the adf4193 and adf4196 product page s. also available is a technical note ( adf4193 - tn - 001, adf4193 loop filter desig n u sing adisimpll ) that outlines a loop filter design procedure that takes full advantage of the new degree of freedom in the filter design that the differential amplifier and loop filter switches provide. 09450-037 r set 23 mux out d gnd 1 16 sw2 27 sw gnd 28 sw1 29 cp out+ 30 cp out? 26 ref in 11 rf in? 5 rf in+ 6 clk 17 sd gnd 14 a gnd 1 4 a gnd 2 22 lock detect out data 18 le 19 reference 104mhz, 5dbm adf4196 sdv dd 15 dv dd x 8, 10, 13 v p 1 20 v p 2 24 av dd 7 v p 3 32 9 d gnd 2 12 d gnd 3 21 r set 2.40k? ain+ ain? 31 25 3 2 a out sw3 integrated differential amplifier c1b 120pf c1a 120pf c3 470pf 100nf 1 cmr ct 30pf r1b1 820? r1b2 6.20k? r1a2 6.20k? r1a1 820? c2b 1.20nf c2a 1.20nf r3 62? r2 1.80k? l1 2.2mh sirenza vco190-1843t 38mhz/v 100pf 100pf 1nf 1nf 51? 51? 100nf 10f + 10f + 100nf 100nf 100nf 100pf 10f + 100nf 100nf 3v 5v 5.5v 10pf 100pf 18? 18? 18? rf out figure 37 . lo for dcs1 800 tx using the adf4196
data sheet adf4196 rev. b | page 27 of 28 interfacing the adf4196 has a simple spi-compatible serial interface for writing to the device. the clk, data, and le pins control the data transfer. when le goes high, the 24 bits that have been clocked into the input register on each rising edge of clk are latched into the appropriate register. see figure 2 for the timing diagram and table 6 for the register address table. the maximum allowable serial clock rate is 33 mhz. aduc70xx interface figure 38 shows the interface between the adf4196 and the aduc70xx family of analog microcontrollers. the aduc70xx family is based on an arm7? core, although the same interface can be used with any 8051-based microcontroller. the micro- controller is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4196 needs a 24-bit word. this is achieved by writing three 8-bit bytes from the microcontroller to the device. when the third byte is written, bring the le input high to complete the transfer. when power is first applied to the adf4196 , an initialization sequence is required for the output to become active (see table 9). i/o port lines on the microcontroller are also used to detect lock (mux out configured as lock detect and polled by the port input). when operating in the spi master mode, the maximum spi transfer rate of the aduc7023 , for example, is 20 mbps. this means that the maximum rate at which the output frequency can be changed is 833 khz. if using a faster spi clock, ensure adherence to the spi timing requirements that are listed in table 2. aduc70xx adf4196 spiclk clk data le mux out (lock detect) mosi i/o ports 09450-033 figure 38. aduc70xx -to- adf4196 interface blackfin adsp-bf527 interface figure 39 shows the interface between the adf4196 and the blackfin? adsp-bf527 digital signal processor (dsp). the adf4196 needs a 24-bit serial word for each latch write. the easiest way to accomplish this, when using the blackfin family, is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits, and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. ensure that the clock speeds are within the maximum limits that are outlined in table 2. adsp-bf527 adf4196 sclk clk data le mux out (lock detect) mosi gpio i/o flags 09450-034 figure 39. adsp-bf527 -to- adf4196 interface pcb design guidelines the lands on the chip scale package (cp-32-2) are rectangular. the printed circuit board (pcb) pad for these lands should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. to ensure that the solder joint size is maximized, center the land on the pad. the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb should be at least as large as the exposed pad. to avoid shorting, provide a clearance on the pcb of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, incorporate them into the thermal pad at a 1.2 mm pitch grid. provide a via diameter between 0.3 mm and 0.33 mm, and plate the via barrel with 1 oz copper to plug the via. connect the pcb thermal pad to a gnd 1 or a gnd 2.
adf4196 data sheet rev. b | page 28 of 28 outline dimensions 3.25 3.10 sq 2.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant t o jedec s t andards mo-220-vhhd-2 1 32 8 9 25 24 17 16 coplanarit y 0.08 3.50 ref 0.50 bsc pin 1 indic a t or pin 1 indic a t or 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom sea ting plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq 0.60 max 0.60 max 0.25 min 05-25-20 1 1- a t op view exposed p ad bot t om view figure 40 . 32 - lead lead frame chip scale package [lfcsp_vq ] 5 mm 5 mm body, very thin quad (cp - 32 - 2 ) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description p ackage option adf4196 bcp z ? 40c to + 85c 32- lead lfcsp _vq cp -32-2 adf4196 bcp z - rl7 ? 40c to + 85c 32 - lead lfcsp _vq cp - 32 - 2 eval - adf419 3eb z1 evaluation board (gsm 1800) eval - adf419 3eb z2 evaluation board ( n o vco or loop filt er) 1 z = rohs compliant part. 2 the eval - adf4193ebz1 and eval - adf4193ebz2 evaluation boards are designed to accommodate either the adf419 3 or the adf4196. ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09450 - 0 - 12/11(b)

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